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prism_issue_backend

II1 cycleLatency15 cycles FP32, 17 cycles KulischMemory2 input and 6 output entries per slice, 1 group assembly stage

prism_issue_backend turns a variable-width issue group into independent sixteen-element tiles, executes those tiles in parallel, and rejoins their reduced results. One instance is one issue bank; the core stripes groups across multiple instances.

Contracts

  • Issue group: accepts one compact 512-bit wire payload, lane masks, and one shared prism_tile_meta_t.
  • Issue slices: creates ISSUE_SLICES independent conversion and range-scheduler paths, each with TILE_ELEMENTS lanes.
  • Reduced group: publishes the active tiles together with one sticky accumulation warning.

Contract behavior

  • Activates only the slices required by the input format and final partial group.
  • Expands the compact wire payload into 32-bit arithmetic lanes beside the selected issue bank, after shared ingress buffering and arbitration.
  • Gives every slice its own global first-element index and range state.
  • Uses KULISCH_ACC_W for the single Kulisch representation (279 bits by default); FP32 operations use the parallel binary32 path.
  • Accepts a new full group every cycle when all active slices are ready.
  • Registers the physical slice rotation in an elastic dispatch stage. Wide metadata and element buses remain outside the backpressure path.
  • Stages each active slice in an independent two-entry input queue. Pending bits let ready slices enqueue exactly once while another active slice is stalled. The FIFO write path is local to each physical slice, so a full inactive slice cannot block another slice.
  • Registers each output FIFO head before matching and arbitration. The four FIFO entries plus two registered head entries preserve backpressure without placing asynchronous memory reads on the output ready path.
  • Snapshots the selected physical queue heads before rotating them onto the group output. This separates arbitration from the wide assembly mux while still accepting and emitting one complete group per cycle.
  • Selects completed groups round-robin so sustained traffic on one slice cannot starve completed work on another slice.
  • Exposes one atomic ready/valid transfer for the whole group while allowing its local slice queues to accept on different cycles under backpressure.