4. Results¶
The evaluation asks three questions: how quickly the SINGLE node processes a collective, how much traffic an exact result requires, and how much FPGA logic the current core uses. These pages bring together the measurements and figures from the thesis evaluation chapter.
RTL simulation ≥ 100 Gbit/s
On every input and output of the U280 profile, for all 24 format pairs; the slowest stream, FP32 DATA, sustains 100.98 Gbit/s.
Software estimate 87.2–93.4%
Fewer RESULT-frame bytes with AUTO + adaptive compression than uniform Kulisch, across the four evaluated workload vectors.
FPGA implementation 40.64% LUTs
Post-route use of the one-port U280 board build, which meets timing at 250 MHz with an estimated 13.6 W on chip.
Reading the results¶
| Section | What it establishes |
|---|---|
| Performance | DATA and RESULT throughput, AllReduce response time, final-contribution latency, and the line rate of the U280 profile. |
| Traffic | Native AUTO packet savings and workload-dependent superaccumulator compression. |
| Implementation | Timing, placement, utilization, and power of the U280 board build. |
The performance figures come from RTL simulation. Compression is a software study of a proposed protocol extension. Resource figures come from FPGA implementation reports. On-board throughput, power, and multi-switch operation remain part of the hardware work.
The graphs are the thesis figures, supplied here as zoomable vectors in English and Italian, plus the LUT and power budget of the board build. Each page states the configuration and accounting rules beside its figures.