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prism_range_scheduler

II1 cycleLatency10 cycles arrival, 7 or 10 cycles ordered, 12 cycles KulischMemoryLocal 1W1R RAM

prism_range_scheduler owns the in-flight state for global element ranges. It combines each expected contributor exactly once and publishes a range only after its lane coverage is complete.

Contracts

  • Input tile: accepts operation metadata, 32-bit lane containers, and lane keep bits.
  • Reduced tile: publishes prism_tile_meta_t, reduced binary32 lanes, lane keep bits, and the sticky accumulation-warning flag.
  • Capacity: bounds simultaneous range contexts and contributors through RANGES and CONTRIBUTORS.

Contract behavior

  • Matches a tile internally by operation slot, operation generation, and global range index, or allocates a free range context. The complete protocol key is retained with the range for the emitted result. Slot reuse is legal only after the previous generation has retired from the datapath.
  • Tracks the received lane mask separately for every contributor.
  • Reserves the range while the input is still compact, then carries an admission token through local conversion. The expanded result commits without repeating the associative lookup or waiting in a wide scheduler-entry FIFO. Committed range state is visible to the following request on the next cycle. This preserves II=1 for consecutive Kulisch contributions to the same slot. The Kulisch path pipelines synchronous RAM read, addition, and writeback with local forwarding.
  • Applies FP32_ARRIVAL contributions as accepted, preserves Contributor ID order for FP32_ORDERED, and uses fixed-point accumulation for the Kulisch path.
  • For a complete two-contributor FP32_ORDERED range, submits the ordered pair directly to all sixteen lanes of its issue slice instead of serializing a separate fold step.
  • Handles zero, NaN, positive infinity, and negative infinity consistently across contributors.
  • Saturates the configured Kulisch width on overflow and keeps m_accumulation_inexact sticky.
  • Produces an FP32 arrival result 10 cycles after the final accepted raw contribution and a Kulisch result after 12 cycles when no output stall is present. The ordered path takes 7 cycles for one contributor and 10 cycles for the direct two-contributor pair. Larger ordered groups use a serialized contributor-ID fold; the verified three-contributor latency is 20 cycles. These values include the local two-stage input conversion. Independent operations can enter the arithmetic pipelines on consecutive cycles.
  • Backpressures the compact input boundary when no range context or arithmetic backend is available; the upstream elastic buffer holds the pending tile.