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prism_data_depacketizer

II1 cycleMemory3 beat register reservoir

prism_data_depacketizer removes Ethernet and PRISM DATA headers from a validated frame and presents each issue group as one compact 512-bit wire payload.

Contracts

  • Validated frame: accepts prism_frame_desc_t, prism_ingress_context_t, and their buffered AXI frame.
  • Issue group: publishes prism_tile_meta_t, the compact 512-bit wire payload, and a per-lane mask for the active tiles.
  • Flow control: independently handshakes the frame descriptor and tile stream while keeping them associated.

Contract behavior

  • Uses the validated input format to determine the number of bytes per element.
  • Buffers up to three AXI beats so the 40-byte prefix does not fragment every later 64-byte payload tile.
  • Uses fixed byte extraction for each wire format and a fixed 512-bit reservoir advance for every non-final issue group. The short final group is discarded after transfer. This preserves one input beat per cycle without synthesizing a general per-byte crossbar.
  • Keeps the payload in wire format through the per-port FIFO and issue-bank arbitration. Expansion into 32-bit arithmetic lanes happens only beside the selected issue bank, avoiding a 2048-bit shared ingress path.
  • Computes each group's global first-element index from the chunk index and payload progress.
  • Emits one FP32 tile, two FP16/BF16 tiles, or four INT8 tiles when the configured issue width has sufficient slices.
  • Carries operation, group, contributor, format, route, and warning metadata into every group.
  • Drains the remainder of a frame when no further arithmetic tile can be emitted.