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prism_collective_core

MemoryBRAM frame FIFOs plus local work and job queues

prism_collective_core is the production-independent composition boundary. It connects the ingress, control, reduction, storage, routing, and egress stages without embedding an FPGA-shell interface.

Contracts

  • Per-port ingress AXI streams: accept complete Ethernet frames from the deployment adapter.
  • Per-port egress AXI streams: publish complete CONTROL or RES frames and their logical byte lengths.
  • Local configuration: receive the local MAC vector and the laboratory-extension enable bit.
  • Timebase: consume a one-cycle millisecond_tick for lease and timeout accounting.
  • Build parameters: size ports, queues, control tables, tile elements, shared issue slices, result storage, and the Kulisch accumulator width.

Contract behavior

  • Keeps packet metadata aligned with the corresponding ready/valid data stream.
  • Arbitrates shared control lookup resources across ingress ports and tags each registered response with its requesting port.
  • Stripes groups across NUM_PORTS shared, profile-selectable issue banks, then merges completed groups before shared result conversion and storage.
  • Registers each selected bank input through two elastic stages before its arithmetic backend, adding two cycles while retaining II 1.
  • Applies backpressure through every pipeline boundary instead of dropping an accepted frame.
  • Registers admitted ingress traffic before demultiplexing, adding one cycle while sustaining one beat per cycle and isolating the complete-frame FIFO from depacketizer backpressure.
  • Routes CONTROL responses and collective results to per-port packetizers.
  • Registers result traffic before egress arbitration, adding one cycle while sustaining one beat per cycle and isolating payload prefetch from downstream ready paths.
  • Leaves clock generation, reset synchronization, and shell bus adaptation to the integration wrapper.