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PRISM

PRISM (Precision-aware Reduction In-Switch Module) is an open-source RTL research prototype for “in-network collective” (INC) operations on FPGA-based packet-processing datapaths. The project studies how reduction-oriented collective operations, such as REDUCE_SUM1 aggregation, can be partially offloaded from the host accelerator (CPU/GPU) communication stack into the network data plane itself. In this sense, PRISM is inspired by the same broad direction as Mellanox/NVIDIA SHARP2, which demonstrated that collective reduction processing can be moved into network switching hardware to reduce communication overhead and improve collective latency.

Objective

PRISM is not an attempt to clone SHARP or reproduce a commercial InfiniBand/Ethernet switch ASIC. It is an inspectable FPGA research vehicle for one question: how can a switch-like datapath combine line-rate packet forwarding, streaming collective accumulation, and reproducible floating-point arithmetic?

The datapath exposes a 512-bit AXI-Stream interface. OpenNIC is the reference platform for the first prototype: it provides the FPGA shell in which PRISM is synthesized and the integration with the NIC, host drivers, and software.

From a numerical perspective, PRISM focuses on reproducible floating-point reductions. Conventional FP32 reductions are sensitive to operand ordering because floating-point addition is not associative; different reduction trees or scheduling orders may produce different bit-level results. PRISM therefore compares the baseline FP32_ARRIVAL profile against a Kulisch-style3 long-accumulator approach, with the goal of studying the area, latency, throughput, and reproducibility trade-offs of exact or near-exact accumulation in a streaming network datapath.

The target architecture is a reusable, port-parameterized collective core. It implements buffering, backpressure, CONTROL, reduction, result routing, and replication; OpenNIC profiles adapt the same RTL to one U50 CMAC or two U280 CMACs. Forwarding, VOQs, a general crossbar, and multi-switch aggregation remain later integration work.

The latest source code is available from the PRISM GitHub repository.

Citation

If you use PRISM in your project, please cite the repository and/or the thesis:

@misc{prism-repository,
  author = {Cipolletti, Lorenzo},
  title = {PRISM Repository},
  year = {2026},
  howpublished = {\url{https://github.com/uniquadev/prism}},
  note = {Bachelor thesis project repository}
}

@mastersthesis{cipolletti-prism-thesis,
  author = {Cipolletti, Lorenzo},
  title = {Development of Primitive Hardware for Network Computing},
  school = {Sapienza University of Rome},
  year = {2026},
  type = {Bachelor thesis},
  note = {Supervisor: Salvatore Pontarelli; co-supervisor: Daniele De Sensi}
}

Reading guide


  1. MPI Forum, MPI 4.1 Standard, MPI_Reduce. The standard notes that implementations may change reduction order using associativity/commutativity and that this can change results for floating-point addition. https://www.mpi-forum.org/docs/mpi-4.1/mpi41-report/node130.htm 

  2. Mellanox SHARP: Scalable Hierarchical Aggregation and Reduction Protocol. 

  3. Kulisch, Ulrich W. "Computer Arithmetic and Validity: Theory, Implementation, and Applications." Walter de Gruyter, 2002.