1. Introduction¶
MiniSharp is an open-source RTL research prototype for “in-network collective” (INC) on FPGA-based packet-processing datapaths. The project explores how reduction-oriented collective operations, such as reduce aggregation, can be partially offloaded from the host CPU/GPU communication stack into the network data plane itself. In this sense, MiniSharp is inspired by the same broad direction as Mellanox/NVIDIA SHARP, which demonstrated that collective reduction processing can be moved into network switching hardware to reduce communication overhead and improve collective latency. 1
Objective
MiniSharp is not an attempt to clone SHARP, nor does it aim to reproduce the full functionality of a commercial InfiniBand or Ethernet switch ASIC. Instead, it is a compact and inspectable hardware research vehicle for studying the microarchitecture of INC primitives under FPGA constraints. The core question is narrower and more experimental: how can a switch-like RTL datapath support line-rate packet forwarding and streaming collective accumulation while also improving floating-point reproducibility?
The design targets a 512-bit AXI-Stream packet interface and is intended to be mapped onto an FPGA NIC/smartNIC-style shell, such as an OpenNIC-like platform. Its data plane is organized around packet parsing, L2 classification, custom EtherType handling, protocol versioning, Virtual Output Queueing (VOQ), shared packet memory, packet-level egress arbitration, cut-through forwarding, and a streaming collective engine.
From a switching perspective, MiniSharp implements a switch-inspired data-plane skeleton rather than a complete production switch. It includes mechanisms commonly found in high-performance packet switches, such as per-output arbitration, VOQ-style buffering, shared-memory packet storage, backpressure propagation, and packet-level scheduling. However, advanced industrial features such as VLAN processing, ACLs, multicast replication engines, QoS hierarchies, credit-based congestion control, ECN/PFC, telemetry, fault isolation, and production-grade buffer management are intentionally outside the initial scope.
From a numerical perspective, MiniSharp focuses on reproducible floating-point reductions. Conventional FP32 reductions are sensitive to operand ordering because floating-point addition is not associative; different reduction trees or scheduling orders may produce different bit-level results. MiniSharp therefore compares a baseline FP32 accumulation path against a Kulisch-style long-accumulator approach, with the goal of studying the area, latency, throughput, and reproducibility trade-offs of exact or near-exact accumulation in a streaming network datapath. 2
The latest source code is available from the MiniSharp GitHub repository.
1.2 Citation¶
If you use MiniSharp in your project, please cite the repository and/or the thesis:
@misc{mini-sharp-repository,
author = {Cipolletti, Lorenzo},
title = {Mini-Sharp Repository},
year = {2026},
howpublished = {\url{https://github.com/uniquadev/mini-sharp}},
note = {Bachelor thesis project repository}
}
@mastersthesis{cipolletti-mini-sharp-thesis,
author = {Cipolletti, Lorenzo},
title = {Development of Primitive Hardware for Network Computing},
school = {Sapienza University of Rome},
year = {2026},
type = {Bachelor thesis},
note = {Supervisor: Salvatore Pontarelli; co-supervisor: Daniele De Sensi}
}
1.3 Reading paths¶
First pass
Start with 2. Getting Started, then read the 3. Architecture overview.
Hardware view
Move through 3.1 Protocol, 3.2 Pipeline pages.
Thesis evidence
Track open experiments in 4. Results and keep the writing plan visible in 5. Future Works.